Meta MTIA 300–500: four AI chips in two years
Meta disclosed MTIA 300, 400, 450 and 500. We analyse chiplets, a 72-accelerator domain, HBM, MX4/MX8, the software stack and benchmark caveats.
- AUTHOR
- Karol Rapacz / CEO of Breachroad · OSCP · PNPT
- PUBLISHED
- 11 March 2026
- READING TIME
- 12 min read
- TOPIC
- AI Security
On 11 March 2026, Meta detailed four generations of in-house accelerators: MTIA 300, 400, 450 and 500. The company said it had already deployed hundreds of thousands of earlier MTIA chips, while the new generations were deployed or planned for 2026–2027. Modular chiplets and a shorter cadence are intended to follow changing recommendation, training and generative-AI workloads.
MTIA 300 runs recommendation training in production. MTIA 400 extends coverage to GenAI with a 72-accelerator scale-up domain; Meta completed lab testing and planned data-centre deployment. MTIA 450, scheduled for mass deployment in early 2027, doubles HBM bandwidth over 400 and adds inference-focused low precision. MTIA 500, also planned for 2027, adds another 50% HBM bandwidth.
Why inference is memory-bound
During token generation, model weights are repeatedly read and arithmetic intensity can be lower than training. HBM bandwidth may therefore matter more than peak FLOPS. Capacity also keeps model weights and KV cache local, reducing cross-chip communication.
Meta reported 4.5× HBM bandwidth and 25× compute growth from MTIA 300 to 500, but the compute comparison moves from MX8 to MX4. Those formats differ, so this is not proof of a 25× speed-up for one application. Model, batch size, sparsity, compiler and network determine reality.
Hardware needs a mature software stack
An accelerator is useful only when frameworks schedule operators, debug failures and maintain compatibility. Meta cited PyTorch, vLLM and Triton integration, OCP work, plus a Rust userspace driver and firmware. In-house silicon also creates a compiler, runtime, firmware and telemetry supply chain.
Security requirements should include:
- signed firmware and controlled updates,
- tenant memory isolation and post-job clearing,
- runtime and model attestation,
- error logs without prompt data,
- SBOMs for compilers and communication libraries.
Comparing accelerators
Measure completed tasks per watt, p95 latency, quality at the chosen quantisation, compilation time and long-run stability. Include operator migration cost and the ability to fall back to another backend. Our Nemotron and NVFP4 analysis discusses low-precision caveats.
MTIA demonstrates vertical integration across model, runtime, chip and data centre. It may lower cost, but vendor claims still need independent validation and portability planning. The whole task matters more than the chip.
What a 72-accelerator scale-up domain means
Scale-up uses a fast fabric so a large model behaves as if it had one logical resource. Bandwidth, latency and collectives such as all-reduce and all-to-all are critical. Domain size alone does not show efficiency; topology, bisection bandwidth and tensor or expert partitioning matter.
One failed component can interrupt the job, so runtime needs fault detection, checkpoints and degradation. For inference, the scheduler should route around a failed chip without losing every session. Telemetry must distinguish model, compiler, HBM and interconnect failures.
Low precision and quality
MX8 and MX4 reduce memory cost and raise throughput, while quantisation may affect layers unevenly. Evaluate real tasks, long context, less common languages and tool calls, not only perplexity. A small argument-quality drop can create a large agent side effect.
Version the quantisation recipe and calibration dataset. Two artefacts with one model name but different scales are different deployments. Registry records should bind weights, format, compiler build and accelerator.
Multi-tenant security
An inference accelerator may serve different users. Clear HBM and buffers, isolate DMA/IOMMU and prevent uncontrolled cache reuse. Side channels or scheduler defects can expose prior context without model access.
Does in-house silicon mean full supply-chain control? No. Partners, EDA, memory, packaging and firmware remain. Control increases, while the chain stays layered.
Compute-buyer conclusion
A cloud customer may never select MTIA directly but will experience it through product price and latency. Require stable backend-independent SLOs and evaluations. Providers should disclose quantisation or architecture changes when they may affect quality, security or data residency.
Primary source: Meta AI — Four MTIA Chips in Two Years.
